1. Technical Field
This disclosure relates to frequency detection and, more particularly, to frequency detecting mechanisms for clock generation circuits.
2. Description of the Related Art
Many types of electronic systems use clock generation circuits to generate clock signals. Some clock generation circuits use a reference clock to generate higher or lower frequency clock signals. One such circuit is referred to as a phase locked loop (PLL) circuit. An analog PLL typically includes a feedback path. If the PLL is used as a frequency multiplier, the feedback path includes a divider. A reference clock is mixed with the feedback signal to feed a phase detector. The output of the phase detector may be low pass filtered and used as a reference voltage of a voltage controlled oscillator (VCO). The output of the VCO may be used as the PLL output. The PLL is designed to provide an output clock that is phase locked with the input reference clock.
There are many ways to measure the frequency of the output clock of a clock generation circuit such as a PLL. For example, an oscilloscope, or a frequency meter may be used. However, when the clock generation circuit is manufactured on an integrated circuit (IC), it may not be cost effective to directly measure the output clock signal during production testing of the IC for a variety of reasons. More particularly, in some cases, IC pins may not be available for that purpose, unless special test mode interfaces are used. This type of testing may significantly slow production testing. Alternatively, it may be more costly to purchase an automated tester to measure the frequency if the frequency is especially high.